This invention relates to a high-speed read-out semiconductor memory equipped with high-speed read-out function, and more particularly to that able to be driven with a smaller power supply.
FIG. 4 is a block diagram illustrating an example of a conventional high-speed read-out semiconductor memory, comprising;
memory cell units 22, 23, 35 and 36, PA1 a first address generator 17 for generating upper bits AD3 to ADn of read-out addresses for the memory cell units 22, 23, 35 and 36, PA1 an X-decoder 20 and a Y-decoder 21 for selecting consecutive four words of memory cells from the memory cell units 22, 23, 35 and 36 indicated by the upper bits AD3 to ADn of the read-out addresses, by activating a word line of the memory cell units and controlling Y-selectors 24, 25, 33 and 34, each of which selects a word of bit lines of each of the memory cells 22, 23, 35 and 36 respectively, PA1 sense amplifier units 4, 5, 31 and 32, each of which senses and amplifies logic of a word of memory cells delivered through each of the Y-selectors 24, 25, 33 and 34, respectively, PA1 latch units 2, 3, 37 and 38 for latching read-out data of the sense amplifier units 4, 5, 31 and 32 respectively, PA1 a two bit decoder 26 for controlling one of the latch units 2, 3, 37 and 38 to output its latching data to an output circuit 16 for buffering the read-out data for external output, according to logic of lower two bits AD1 and AD2 of the read-out addresses generated by a second and a third address generators 18 and 19, and PA1 a pulse generator 1 for generating a sense amplifier enabling signal DE for controlling the sense amplifier units 4, 5, 31 and 32 and a latch timing signal DL for controlling latch units 2, 3, 37 and 38 at every timing when logic of any of the upper bits AD3 to ADn of the read-out addresses changes. PA1 four units of memory cells; PA1 an address generator for generating an read-out address of a word to be read out from said four units of memory cells; PA1 selecting means for selecting four words of memory cells according to said read-out address, each of said four words being selected from each of said four units of memory cells and each of addresses of said four words having the same upper bits than a second lower bit thereof with each other; PA1 four sense amplifier units, each of said four sense amplifier units sensing and amplifying data stored in each of said four words of memory cells selected by said selecting means; PA1 four latch units, each of said four latch units latching a word of data sensed and amplified by each of said four sense amplifier units; PA1 a decoder for controlling one of said four latch units to output data latched therein, decoding and according to logic of lower two bits of said read-out address; PA1 a pulse generator for generating a sense amplifier enabling signal and a latch timing signal, said latch timing signal becoming active in a latter part of a period when said sense amplifier enabling signal becomes active following every timing when upper bits than second lower bit of said read-out address differ from those of a preceding read-out address of said read-out address; and PA1 a selective delay circuit for generating two pairs of an enabling signal and a timing signal according to logic of a second lower bit of said read-out address when upper bits than said second lower bit of said read-out address differ from those of a preceding read-out address of said read-out address,
FIG. 5 is a timing chart illustrating operation of the conventional high-speed read-out semiconductor memory of FIG. 4.
When consecutive addresses are given for read-out a block of data and logic of one, which should be AD3 in the case, of upper bits AD3 to ADn of the addresses are changed at a timing T0 shown in FIG. 5, for example, the pulse generator 1 generates a sense amplifier enabling signal DE and a latch timing signal DL following the timing T0 in that order as shown in FIG. 5.
Every of the sense amplifier units 4, 5, 31 and 32 becomes active during the sense amplifier enabling signal DE is at LOW level and detects and amplifies logic of a word of memory cells delivered through corresponding Y-selector selected by the X and Y-decoders 20 and 21. Thus, data of four words, of which upper bits of each address are the same, are read out at once by the sense amplifier units 4, 5, 31 and 32 as shown in FIG. 5.
Then the latch timing signal DL becomes at LOW level during the sense amplifier enabling signal DE remains at LOW level for controlling every of the latch units 2, 3, 37 and 38 to latch data read out by corresponding each of the sense amplifier units 4, 5, 31 and 32.
These data of four words latched by the latch units 2, 3, 37 and 38 are output after buffered for external output at the output circuit 16, consecutively in the case, according to and following a little after logic of lower two bits AD1 and AD2 of the read-out addresses indicated consecutively at timings T0, T1, T2 and T3, as shown in FIG. 5.
Thus, in the high-speed read-out semiconductor memory of FIG. 4, when a sequence of read-out addresses are given, data of a first word having an address of which logic of upper bits AD1 to ADn is changed are output after processes of memory cell selection, data detection, data latching, selecting a latch unit and data buffering for external output.
But as for data of following words having the same logic of upper bits AD3 to ADn of their read-out addresses, three words when consecutive addresses are given, they can be read out only with processes for selecting a latch unit and data buffering for external output, providing the high-speed read-out.
Here, pulse width of the sense amplifier enabling signal DE is prepared for suppressing current consumed by the sense amplifier units 4, 5, 31 and 32 to a minimum value.
The current consumed by the sense amplifier units 4, 5, 31 and 32 adds up to more than half of the total power dissipation of the high-speed read-out semiconductor memory. And further, peak value of the current Ic of FIG. 5 consumed at once in a short period by the sense amplifiers increases in proportion to number of sense amplifiers, which is given by product of bit width of a word and number of words to be read out at once by the sense amplifier units, four in the example of the high-speed read-out semiconductor memory of FIG. 4.
Therefore, a power supply having a sufficient capacity must be provided for driving a large number of sense amplifiers at once in the conventional high-speed read-out semiconductor memory.
This is a problem.